Vertical NAND channel configurations have been investigated to increase the density of non-volatile memories. One such vertical NAND channel structure is discussed in “Bit Cost Scalable Technology With Punch and Plug Process For Ultra High Density Flash Memory,” by H. Tanaka et al. in Symp, on VLSI Tech. Dig., pp 14˜15(2007). Meanwhile, US Patent Publication No. 2009-0121271 entitled ‘Vertical-type non-volatile memory devices’ discloses a vertical NAND having a metal gate and a method of the same. The disclosures of the above article and US publication are incorporated herein in their entirety.